@matias-eduardo matias-eduardo starred ZipCPU/zipcpu · May 16, 2025 23:48
ZipCPU/zipcpu

A small, light weight, RISC CPU soft core

Verilog 1.4k Updated Feb 6

@matias-eduardo matias-eduardo starred milanvidakovic/FPGAComputer32 · May 7, 2025 20:22
milanvidakovic/FPGAComputer32

Verilog 3 Updated Feb 7, 2022

@matias-eduardo matias-eduardo starred johnwinans/Verilog-Examples · April 29, 2025 00:29
johnwinans/Verilog-Examples

Verilog 40 Updated Mar 1

@jacksonwb
jacksonwb starred UofT-HPRC/fpga-bpf Nov 24, 2022
UofT-HPRC/fpga-bpf

A versatile Wireshark-compatible packet filter, capable of 100G speeds and higher. Also known as FFShark

Verilog 31 Updated Jul 10

@SuperSpyTX
SuperSpyTX starred Ownasaurus/Ultra64 Sep 20, 2021
Ownasaurus/Ultra64

So you want to control 64 N64s at once?

Verilog 1 Updated Sep 19

@akharrou
akharrou starred rj45/rj32 Sep 7, 2021
rj45/rj32

A 16-bit RISC CPU with 32 instructions built with Digital for running on an FPGA.

Verilog 10 Updated Aug 20

@matias-eduardo
matias-eduardo starred osresearch/spispy Aug 3, 2020
osresearch/spispy

An open source SPI flash emulator and monitor

Verilog 190 Updated Aug 3

@scollet1
scollet1 starred hrvach/fpg1 Feb 7, 2019
hrvach/fpg1

PDP-1 FPGA implementation in Verilog, with CRT, Teletype and Console.

Verilog 69 Updated Feb 7